3um Pitch, 1um Active Diameter SPAD Arrays in 130nm CMOS Imaging Technology
نویسندگان
چکیده
A shared well 4x4 SPAD array test structure with 3m pitch is realized in a 130nm CMOS image sensor technology. The SPADs have 150Hz median DCR at room temperature at 1V excess bias, 15% peak PDP and 176ps FWHM timing jitter both at 3V excess bias.
منابع مشابه
3m Pitch, 1m Active Diameter SPAD Arrays in 130nm CMOS Imaging Technology
A shared well 4x4 SPAD array test structure with 3m pitch is realized in a 130nm CMOS image sensor technology. The SPADs have 150Hz median DCR at room temperature at 1V excess bias, 15% peak PDP and 176ps FWHM timing jitter both at 3V excess bias.
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